SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

Author: Voodoogrel Nikoktilar
Country: Albania
Language: English (Spanish)
Genre: Business
Published (Last): 22 March 2014
Pages: 89
PDF File Size: 7.51 Mb
ePub File Size: 6.11 Mb
ISBN: 527-8-72212-180-2
Downloads: 14537
Price: Free* [*Free Regsitration Required]
Uploader: Jukinos

Check for the less congested areas and increasing the spacing of the nets.

Crystal growth and doping 2. This makes MOS dynamic circuits faster.

What are the different methods of programming of PALS? Power dissipation is due to circuit switching to charge and discharge the output load capacitance at a particular node at operating frequency is called dynamic power dissipation. Differentiate between witn and channel less gate array. Routing is done using spaces Routing is done using the area of transistors unused Logic density is less Logic density is higher 6.

This is used in circuits where it is impossible to fault every node in the circuit. Channeled gate array Channel less gate array Only the interconnect is customized Only the top few mask layers are customized The interconnect uses predefined No predefined areas are set aside for spaces between rows of base cells routing between cells.

What is the difference between latches and flip flops based designs? Draw the basic CMOS inverter circuit. The interconnect uses predefined spaces between rows of base cells. Give the different types of CMOS process? The carry skip circuitry consists of two logic gates. What are the advantages of CMOS process? Thin oxide construction 3.


Give the variety of Integrated Circuits? What is called static and dynamic sequencing element?

EC VLSI DESIGN Important Part A 2 Mark Part B 16 Mark Question Bank

Other adder structures use logic optimizations to increase the performance carry bypass, carry select, carry look ahead. State the different types of CMOS processes. It is an analytical method used to estimate the RC delay in a network.

Log In Sign Up. In this circuit realization the PMOS network is identical to the NMOS network rather than being the conduction complement, so the topology is called a mirror adder. It makes sense to take this approach only if there wihh no suitable existing cell libraries available that can be used for the entire design.


Useful skew is a concept of delaying the capturing flip flop clock path, this approach helps in meeting setup requirement within the launch and capture timing path. Verilog is a general purpose hardware descriptor language.

Write notes on functionality tests? The width of the MOS transistor can be increased to reduce delay this is known as gate sizing, which will be discussed later in more details.

If it is true 1 or a non-zero value true- statement is executed. Explain the basic operation of a 2 phase dynamic circuit.


What are the categories of testing? Read operation is followed by restoration operation. Write down the expression to obtain delay for N bit carry bypass adder. Nodes are randomly selected and ef2354.

Low input impedance 5. Pipelining is a popular design technique often used to accelerate the operation of the data path in digital processors. All the partial products are computed in parallel, and then collected through a cascade of Carry Save Adders. Enter the email address you signed up with and we’ll email you a reset link.

Give some circuit maladies to overcome the defects? What are different generations of integration circuits? What are the different MOS layers? Define local skew, global skew, and useful skew. Give the different symbols for transmission gate. Low power dissipation 2. Routing is done using the spaces Routing is done using the area of transist unused.

Xnswers amount of time needed for a change in a logic input to result in an initial change at an output, that is the combinational logic is guaranteed not to show any output change in response to an input change before fed time units have passed. A Latch is Level Sensitive A flip flop is mrks triggered.

Low delay sensitivity to load. Skip to main content.

Author: admin