January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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DDR2 SDRAM – Wikipedia

By using this site, you agree to the Terms of Use and Privacy Policy. From Wikipedia, the free encyclopedia. By using this site, you agree to the Terms of Use and Privacy Policy. The specification defines the two common units of information: The specirication notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits.

The standards specify memory module label formats for end-user markets. This packaging change was necessary to maintain signal integrity at higher bus speeds. DDR2 was introduced in the second quarter of at two initial clock rates: DDR2 started to become competitive against the older DDR standard by the end ofas modules with lower latencies dxr2 available. Please update this article to reflect jdeec events or newly available information.

This article needs to be updated. The definitions of kilo, giga, and mega based on powers of two are included only to reflect iedec usage.

Retrieved August 25, These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates. Views Read Edit View history. DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers.


This page was last edited on 11 Januaryat Retrieved from ” https: The standards specify the physical and electrical characteristics of the modules, and include the data for computer simulations of the memory module operating in a system.

The documentation of modern memory modules, such as the standards for the memory ICs [4] and a reference design of the module [5] requires over one hundred pages. The lower memory specificatin frequency may also enable power reductions in applications that do not require the highest available data rates.

Views Read Edit View history. Dynamic random-access memory DRAM. JEDEC standards and specificaion are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper jecec for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.

Retrieved from ” https: This page was last edited on 2 Augustat However, latency is greatly increased as a uedec. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards. During an access, four bits were read or written to or from a four-bit-deep prefetch queue.

From Wikipedia, the free encyclopedia. An alternative system is found in Amendment 2 to IEC It jeec severe overheating issues due to the nominal DDR voltages. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

This committee dcr2 of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, such as video card and personal computer makers. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name.



These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. This queue received or transmitted its data over the data bus in two data bus clock cycles each clock cycle transferred two bits of data. The purpose of the standard is to promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry.

Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the jeedc latency.


Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage 1. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use “GDDR2”.

In other projects Wikimedia Commons. Bandwidth is calculated by taking transfers per second and multiplying by eight. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency. In addition to double pumping the data bus as in DDR SDRAM transferring data on the rising and falling edges of the bus clock signalDDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus.

Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance. The specification contains definitions of the commonly used prefixes kilomegaand giga usually combined with the units byte and bit to designate multiples of the units.

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